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Analog Layout Engineer
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- Posted 12 days ago
- Be among the first 10 applicants
Job Description
Project Role : Analog Layout Engineer
Project Role Description : Design the physical layout of analog circuits, ensuring proper component placement and routing for optimal performance. Address parasitic effects, signal integrity, and power distribution to meet design specifications. Collaborate to ensure the layout meets functional, electrical, and manufacturing requirements.
Must have skills : Analog Layout Design
Good to have skills : NA
Minimum 3 Year(s) Of Experience Is Required
Educational Qualification : 15 years full time education
Summary:
As an Analog Layout Engineer, your day involves crafting the physical design of analog circuits with careful attention to component placement and routing to achieve the best possible performance. You will focus on mitigating parasitic effects, maintaining signal integrity, and ensuring efficient power distribution. Collaboration with cross-functional teams is essential to guarantee that the layout aligns with functional, electrical, and manufacturing standards, resulting in a robust and manufacturable design solution.
Roles & Responsibilities:
Project Role Description : Design the physical layout of analog circuits, ensuring proper component placement and routing for optimal performance. Address parasitic effects, signal integrity, and power distribution to meet design specifications. Collaborate to ensure the layout meets functional, electrical, and manufacturing requirements.
Must have skills : Analog Layout Design
Good to have skills : NA
Minimum 3 Year(s) Of Experience Is Required
Educational Qualification : 15 years full time education
Summary:
As an Analog Layout Engineer, your day involves crafting the physical design of analog circuits with careful attention to component placement and routing to achieve the best possible performance. You will focus on mitigating parasitic effects, maintaining signal integrity, and ensuring efficient power distribution. Collaboration with cross-functional teams is essential to guarantee that the layout aligns with functional, electrical, and manufacturing standards, resulting in a robust and manufacturable design solution.
Roles & Responsibilities:
- Expected to perform independently and become an SME.
- Required active participation/contribution in team discussions.
- Contribute in providing solutions to work related problems.
- Review and analyze design specifications to develop effective layout strategies.
- Ensure compliance with design rules and manufacturing constraints throughout the layout process.
- Assist junior team members by sharing knowledge and providing guidance on layout best practices.
- Continuously update and improve layout methodologies to enhance design quality and efficiency.
- Must To Have Skills: Proficiency in Analog Layout Design.
- Strong understanding of parasitic extraction and its impact on circuit performance.
- Experience with layout verification tools and design rule checking processes.
- Ability to optimize power distribution networks within analog layouts.
- Familiarity with signal integrity challenges and techniques to mitigate noise and interference.
- Skilled in collaborating with circuit designers and manufacturing teams to ensure design feasibility.
- The candidate should have minimum 3 years of experience in Analog Layout Design.
- This position is based at our BDC6F - SEZ location.
- A 15 years full time education is required.
More Info
Key Skills
About Company
Skills:
Analog Layout, Design for manufacturability and testing requirements, Analog circuit design principles, Parasitic extraction and mitigation techniques
Skills:
matching , Electromigration (EM), Routing, Shielding coupling crosstalk, DC-DC Converter Layout Development, Floorplan optimization, Cadence Virtuoso Editor, IR-drop, Active passive parasitic devices, Analog Layout Design, ESD Latch-up, Calibre, Mixed-Signal Layout Design, BCD Technology, Effort area estimation, Physical verification sign-off, DRC, Layout checks, Analog Layout fundamentals, LVS
Skills:
Synopsys IC Validator, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, Cadence Pegasus, high-speed analog and mixed-signal layout design, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, DRC, parasitic optimization, reliability rules
Skills:
ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques
Skills:
shielding , ESD latch-up prevention, Analog Custom Layout Design, Guard rings, TI Texas Instruments project environment, Cadence Virtuoso, Matching symmetry, Layout verification tools, Common centroid, Advanced process nodes foundry rules, DRC LVS ERC EM IR checks