Analog Layout Engineer
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Job Description
Job Title: Analog Layout Engineer
Experience: 5+ Years
Location: Bangalore
Job Description
We are looking for an experienced Analog Layout Engineer with 5+ years of experience in custom/analog layout design. Candidate should have strong hands-on experience in TI (Texas Instruments) project environment / TI-based project exposure, along with expertise in layout implementation, verification, and tapeout support for analog and mixed-signal blocks.
Key Responsibilities
Experience: 5+ Years
Location: Bangalore
Job Description
We are looking for an experienced Analog Layout Engineer with 5+ years of experience in custom/analog layout design. Candidate should have strong hands-on experience in TI (Texas Instruments) project environment / TI-based project exposure, along with expertise in layout implementation, verification, and tapeout support for analog and mixed-signal blocks.
Key Responsibilities
- Work on Analog / Custom Layout for blocks such as PLL, ADC, DAC, LDO, Bandgap, SRAM, IO, and other mixed-signal circuits
- Perform layout floorplanning, device matching, routing, shielding, and parasitic-aware layout design
- Ensure layout follows DRC, LVS, ERC, and EM/IR design rules and quality standards
- Collaborate with circuit designers, verification, and PV teams for layout closure
- Handle block-level and top-level layout integration
- Support tapeout activities and signoff closure
- Optimize layout for area, performance, reliability, and manufacturability
- 5+ years of experience in Analog / Custom Layout Design
- Hands-on experience in TI project / Texas Instruments project environment
- Strong knowledge of matching, symmetry, shielding, common centroid, guard rings, ESD, latch-up prevention
- Experience in DRC, LVS, ERC, EM/IR checks and fixing layout issues
- Good understanding of analog and mixed-signal design concepts
- Experience with Cadence Virtuoso and related layout verification tools
- Familiarity with advanced process nodes / foundry rules
More Info
Key Skills
ESD latch-up prevention
Analog Custom Layout Design
Guard rings
TI Texas Instruments project environment
Matching symmetry
Layout verification tools
Common centroid
Advanced process nodes foundry rules
DRC LVS ERC EM IR checks
About Company
Skills:
Layout verification tools, Design rule checking processes, Analog Layout Design, Parasitic Extraction
Skills:
matching , Electromigration (EM), Routing, Shielding coupling crosstalk, DC-DC Converter Layout Development, Floorplan optimization, Cadence Virtuoso Editor, IR-drop, Active passive parasitic devices, Analog Layout Design, ESD Latch-up, Calibre, Mixed-Signal Layout Design, BCD Technology, Effort area estimation, Physical verification sign-off, DRC, Layout checks, Analog Layout fundamentals, LVS
Skills:
FinFET GAA layout concepts, Cadence Virtuoso Custom Layout, PEX and post-layout simulation correlation, matching shielding guard rings isolation and parasitic optimization, Calibre PVS, advanced-node analog custom layout
Skills:
reliability driven layout practices, Calibre, analog mixed-signal IC layout, PEX, DRC, parasitic-aware layout, antenna rules, post-layout simulation correlation, LVS, Cadence Virtuoso
Skills:
Synopsys IC Validator, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, Cadence Pegasus, high-speed analog and mixed-signal layout design, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, DRC, parasitic optimization, reliability rules