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Analog Layout Engineer
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- Posted 16 days ago
- Be among the first 10 applicants
Job Description
Project Role : Analog Layout Engineer
Project Role Description : Design the physical layout of analog circuits, ensuring proper component placement and routing for optimal performance. Address parasitic effects, signal integrity, and power distribution to meet design specifications. Collaborate to ensure the layout meets functional, electrical, and manufacturing requirements.
Must have skills : Analog Layout Design
Good to have skills : NA
Minimum 5 Year(s) Of Experience Is Required
Educational Qualification : 15 years full time education
Summary:
As an Analog Layout Engineer, a typical day involves designing the physical layout of analog circuits with careful attention to component placement and routing to achieve optimal circuit performance. The role requires addressing challenges such as parasitic effects, signal integrity, and power distribution to ensure the design meets all necessary specifications. Collaboration with various teams is essential to verify that the layout aligns with functional, electrical, and manufacturing requirements, ensuring a seamless transition from design to production. This position demands a thoughtful and detail-oriented approach to create efficient and reliable analog circuit layouts.
Roles & Responsibilities:
Project Role Description : Design the physical layout of analog circuits, ensuring proper component placement and routing for optimal performance. Address parasitic effects, signal integrity, and power distribution to meet design specifications. Collaborate to ensure the layout meets functional, electrical, and manufacturing requirements.
Must have skills : Analog Layout Design
Good to have skills : NA
Minimum 5 Year(s) Of Experience Is Required
Educational Qualification : 15 years full time education
Summary:
As an Analog Layout Engineer, a typical day involves designing the physical layout of analog circuits with careful attention to component placement and routing to achieve optimal circuit performance. The role requires addressing challenges such as parasitic effects, signal integrity, and power distribution to ensure the design meets all necessary specifications. Collaboration with various teams is essential to verify that the layout aligns with functional, electrical, and manufacturing requirements, ensuring a seamless transition from design to production. This position demands a thoughtful and detail-oriented approach to create efficient and reliable analog circuit layouts.
Roles & Responsibilities:
- Expected to be an SME, collaborate and manage the team to perform.
- Responsible for team decisions.
- Engage with multiple teams and contribute on key decisions.
- Provide solutions to problems for their immediate team and across multiple teams.
- Lead design reviews and provide constructive feedback to improve layout quality and efficiency.
- Coordinate cross-functional communication to align project goals and timelines.
- Mentor junior engineers to support their professional growth and technical development.
- Must To Have Skills: Proficiency in Analog Layout Design.
- Strong knowledge of analog circuit design principles and layout techniques.
- Experience with layout verification tools and methodologies to ensure design accuracy.
- Ability to analyze and mitigate parasitic effects impacting circuit performance.
- Familiarity with power distribution networks and signal integrity considerations in analog layouts.
- Skilled in collaborating with cross-disciplinary teams to meet design and manufacturing requirements.
- The candidate should have minimum 5 years of experience in Analog Layout Design.
- This position is based at our BDC6F - SEZ office.
- A 15 years full time education is required.
More Info
Key Skills
Power distribution networks
Layout verification tools and methodologies
Signal integrity considerations
Analog Layout Design
Analog circuit design principles
About Company
Skills:
Layout verification tools, Design rule checking processes, Analog Layout Design, Parasitic Extraction
Skills:
matching , Electromigration (EM), Routing, Shielding coupling crosstalk, DC-DC Converter Layout Development, Floorplan optimization, Cadence Virtuoso Editor, IR-drop, Active passive parasitic devices, Analog Layout Design, ESD Latch-up, Calibre, Mixed-Signal Layout Design, BCD Technology, Effort area estimation, Physical verification sign-off, DRC, Layout checks, Analog Layout fundamentals, LVS
Skills:
Synopsys IC Validator, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, Cadence Pegasus, high-speed analog and mixed-signal layout design, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, DRC, parasitic optimization, reliability rules
Skills:
ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques
Skills:
shielding , ESD latch-up prevention, Analog Custom Layout Design, Guard rings, TI Texas Instruments project environment, Cadence Virtuoso, Matching symmetry, Layout verification tools, Common centroid, Advanced process nodes foundry rules, DRC LVS ERC EM IR checks