Layout verification tools, Design rule checking processes, Analog Layout Design, Parasitic Extraction

matching , Electromigration (EM), Routing, Shielding coupling crosstalk, DC-DC Converter Layout Development, Floorplan optimization, Cadence Virtuoso Editor, IR-drop, Active passive parasitic devices, Analog Layout Design, ESD Latch-up, Calibre, Mixed-Signal Layout Design, BCD Technology, Effort area estimation, Physical verification sign-off, DRC, Layout checks, Analog Layout fundamentals, LVS

FinFET GAA layout concepts, Cadence Virtuoso Custom Layout, PEX and post-layout simulation correlation, matching shielding guard rings isolation and parasitic optimization, Calibre PVS, advanced-node analog custom layout

reliability driven layout practices, Calibre, analog mixed-signal IC layout, PEX, DRC, parasitic-aware layout, antenna rules, post-layout simulation correlation, LVS, Cadence Virtuoso

Synopsys IC Validator, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, Cadence Pegasus, high-speed analog and mixed-signal layout design, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, DRC, parasitic optimization, reliability rules

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques

shielding , ESD latch-up prevention, Analog Custom Layout Design, Guard rings, TI Texas Instruments project environment, Cadence Virtuoso, Matching symmetry, Layout verification tools, Common centroid, Advanced process nodes foundry rules, DRC LVS ERC EM IR checks