Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage

DDR, Pcie, Ethernet, Arm, RISC-V, Palladium, UCIe, Boot Code, Uvm, coverage-driven verification, systemverilog, Assertions, Zebu, SoC Verification, Veloce, emulation based acceleration, AI-assisted verification flows

python, Perl, System Verilog, test plans for DDR LPDDR IP verification, DDR-IO verification, debug and problem solving, LPDDR JDEC specifications, system verilog programming, coverage driven verification methodology, Uvm

Uart, Usb, Tcl, Ethernet, Perl, Spi, I2c, Shell Scripting, Python, DDR, AHB, UCIe, Siemens QuestaSim, Functional Coverage, systemverilog, MIPI, CXL, DVE, APB, Axi, Cadence Xcelium, Uvm, Constrained Random Verification, Scoreboards, Verdi, Functional Checkers, Synopsys VCS

Perl, Verilog, Python, Cadence Incisive, Xcelium, complex testbenches, Uvm, systemverilog, Synopsys VCS, RTL design concepts, VHDL, formal verification, verification environments, Modelsim

Perl, Python, Test plan development, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, Transaction level modelling, systemverilog, DSP instruction set architectures, Industry standard I/O interfaces, Object-oriented design, AMBA bus protocols, RTL development environments, Baremetal processor environments, Verification methodologies, FPGA and emulation platform knowledge, Formal verification methods, UPF based low power verification, Hardware description languages

Automated Testing, Scripting Languages, systemverilog, Uvm, Verification Planning, Testbench Development, Functional Coverage, Debugging Skills, Signal Processing, FPGA Verification

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog

DDR, Pcie, SV, HBM, Design Verification, CXL, UCIe, Uvm