Design Verification Engineer
Design Verification Engineer
HCL TechBee7-10 Years
- Posted 3 days ago
- Be among the first 10 applicants
Job Description
Looking for a Design Verification Engineer with 7-10 years of ASIC/SoC verification experience, strong expertise in UVM, Formal Verification, SystemVerilog/Verilog, verification environment development, debugging, and scripting (Python/Perl)
Mandatory Skills
- 7 to 10 years of experience in Design Verification (DV) for ASIC/SoC
- Strong hands-on experience in UVM (Universal Verification Methodology)
- Experience in Formal Verification
- Strong knowledge of Verilog/SystemVerilog or VHDL
- Experience in developing and debugging complex testbenches and verification environments
- Strong understanding of RTL design concepts
- Experience with simulation tools such as: Synopsys VCS,Cadence Incisive/Xcelium,ModelSim,
- Scripting experience in Python or Perl
- Strong debugging and root cause analysis skills
Preferred Skills
- Experience with formal verification tools
- Team leadership or mentoring experience
- ASIC/SoC verification at block and subsystem level
- Code reviews and verification methodology improvements
More Info
Key Skills
Cadence Incisive
Xcelium
complex testbenches
Synopsys VCS
RTL design concepts
verification environments
About Company
Skills:
Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage
Skills:
Java, Pcie, Perl, Verilog, Python, System Verilog, coverage-based verification methodology, assertions, Intel Quartus, Uvm, Xilinx Vivado
Skills:
Uart, Usb, Tcl, Ethernet, Perl, Spi, I2c, Shell Scripting, Python, DDR, AHB, UCIe, Siemens QuestaSim, Functional Coverage, systemverilog, MIPI, CXL, DVE, APB, Axi, Cadence Xcelium, Uvm, Constrained Random Verification, Scoreboards, Verdi, Functional Checkers, Synopsys VCS
Skills:
C, Pcie, Perl, Python, Tcl, ONFI, LPDDR, NAND
Skills:
Automated Testing, Scripting Languages, systemverilog, Uvm, Verification Planning, Testbench Development, Functional Coverage, Debugging Skills, Signal Processing, FPGA Verification
Early Applicant