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Design Verification Engineer
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- Posted 3 days ago
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Job Description
Role : Design Verification Engineer
Work Location : Bangalore
Exp : 5+ Years
Industry : Semiconductor
Description
We are seeking a skilled Design Verification Engineer to join our team in India. The ideal candidate will have a strong background in design verification and a passion for ensuring the quality and reliability of complex systems.
Responsibilities
- Develop and execute design verification plans and test cases for complex systems.
- Analyze requirements and specifications to create comprehensive verification strategies.
- Collaborate with design and development teams to resolve issues and ensure quality.
- Utilize verification tools and methodologies to automate testing processes.
- Document test results and provide detailed reports on verification outcomes.
- Participate in design reviews and provide feedback based on verification results.
Skills and Qualifications
- Bachelor's or Master's degree in Electronics, Computer Science, or a related field.
- 5-12 years of experience in design verification or validation, preferably in semiconductor or embedded systems.
- Strong knowledge of verification methodologies such as UVM, OVM, or similar frameworks.
- Proficiency in SystemVerilog, Verilog, or VHDL for hardware description and verification.
- Experience with scripting languages such as Python, Perl, or Tcl for automation.
- Familiarity with tools like ModelSim, QuestaSim, or similar for simulation and verification.
- Understanding of digital design concepts and ASIC/FPGA architecture.
- Excellent analytical and problem-solving skills, with attention to detail.
More Info
Key Skills
Verification Planning
Testbench Development
Functional Coverage
Debugging Skills
FPGA Verification
About Company
Skills:
Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage
Skills:
Java, Pcie, Perl, Verilog, Python, System Verilog, coverage-based verification methodology, assertions, Intel Quartus, Uvm, Xilinx Vivado
Skills:
Uart, Usb, Tcl, Ethernet, Perl, Spi, I2c, Shell Scripting, Python, DDR, AHB, UCIe, Siemens QuestaSim, Functional Coverage, systemverilog, MIPI, CXL, DVE, APB, Axi, Cadence Xcelium, Uvm, Constrained Random Verification, Scoreboards, Verdi, Functional Checkers, Synopsys VCS
Skills:
Verilog, VHDL, simulation debugging, DO-254, traceability validation methodologies, coverage-driven verification, systemverilog
Skills:
Perl, Verilog, Python, Cadence Incisive, Xcelium, complex testbenches, Uvm, systemverilog, Synopsys VCS, RTL design concepts, VHDL, formal verification, verification environments, Modelsim