Lead Physical Design Engineer
Lead Physical Design Engineer
leadsoc technologies pvt ltd6-10 Years
- Posted 11 days ago
- Be among the first 10 applicants
Job Description
Lead Physical Design Engineer
Exp:-6-10yrs
Location-Bengaluru
Job Description:-
- Physical Design Implementation and Methodology: Engage in the implementation of physical design, develop methodologies, and manage sign-off processes.
- Core Design Tasks: Execute floorplanning, clock planning, placement and routing, timing closure, and physical verification to ensure design integrity and performance.
- Project Management: Oversee project schedules, troubleshoot design and workflow issues, and drive methodological improvements and execution strategies.
- Collaborative Teamwork: Work collaboratively with team members to successfully complete projects within designated timelines.
- Programming Skills: Utilize programming skills to effectively complete tasks, with a focus on scripting and automation to enhance workflow efficiency.
- Proficiency in EDA Tools: Demonstrate proficiency in using Electronic Design Automation (EDA) tools such as Innovus, ICC2, LEC, PrimeTime, Calibre, among others.
Requirement:-
- Familiarity with EDA Tools: Proficient in using EDA tools such as ICC, ICCII, and INNOVUS.
- ASIC Flow Knowledge: Well-versed in the ASIC design flow.
- Programming Skills: Proficient in Tcl, Perl, scripting, C, and C++ programming languages.
- Strong Communication Skills: Excellent communication abilities.
- Proactive and Responsible: Highly proactive, enthusiastic, and responsible.
- Large-Scale Design Experience: Experience handling designs with more than 2 million instance counts is preferred.
- Top-Level Physical Design and Advanced Node Experience: Experience in top-level physical design and advanced node tapeout is highly desirable.
More Info
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Key Skills
Clock Planning
Placement and Routing
Physical Design Implementation
About Company
Skills:
Perl scripting, Tcl Scripting, Python, Sta, setup hold analysis, floorplanning, CTS routing, Cadence Innovus, physical optimization, LVS, MMMC-based implementation, full-chip Physical Design, ECO implementation, physical and timing ECOs, Dft, RTL synthesis, Timing Closure, DRC, Placement
Skills:
routing, Tcl Scripting, Shell scripting, Python, Perl, MCMM setup hold OCV AOCV POCV, CTS, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, LVS, Power Planning, post-route optimization, IR Drop, STA timing closure, RTL-to-GDSII Physical Design flow, floorplanning, EM Signal Integrity, signoff, Physical Verification, Eco, DRC, Placement, Synopsys ICC2
Skills:
power optimization , Perl Scripting, CTS, Block level PnR convergence, Cadence Innovus, LVS, Physical Implementation, Timing convergence, Physical Verification, Timing Closure, DRC, PDN, STA concepts, Floor-planning, PD implementation of PPA critical Cores, Place And Route, Synopsys ICC2, formal verification, Clocking architecture
Skills:
EM IR understanding and fixes, PnR-Floorplan Macro placement, STA analysis, Util area reduction experiments, ECO cycle, Physical aware Synthesis using FC, PV closure, Density Congestion Timing issues and fixes