Perl scripting, Tcl Scripting, Python, Sta, setup hold analysis, floorplanning, CTS routing, Cadence Innovus, physical optimization, LVS, MMMC-based implementation, full-chip Physical Design, ECO implementation, physical and timing ECOs, Dft, RTL synthesis, Timing Closure, DRC, Placement

routing, Tcl Scripting, Shell scripting, Python, Perl, MCMM setup hold OCV AOCV POCV, CTS, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, LVS, Power Planning, post-route optimization, IR Drop, STA timing closure, RTL-to-GDSII Physical Design flow, floorplanning, EM Signal Integrity, signoff, Physical Verification, Eco, DRC, Placement, Synopsys ICC2

power optimization , Perl Scripting, CTS, Block level PnR convergence, Cadence Innovus, LVS, Physical Implementation, Timing convergence, Physical Verification, Timing Closure, DRC, PDN, STA concepts, Floor-planning, PD implementation of PPA critical Cores, Place And Route, Synopsys ICC2, formal verification, Clocking architecture

EM IR understanding and fixes, PnR-Floorplan Macro placement, STA analysis, Util area reduction experiments, ECO cycle, Physical aware Synthesis using FC, PV closure, Density Congestion Timing issues and fixes