test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, equivalence check DFT DRC rules, simulating test vectors, ATPG coverage analysis, Cadence Encounter Test, DFTMax, timing fixes corrective actions for timing violations, ASIC DFT

Analog Layout, Design for manufacturability and testing requirements, Analog circuit design principles, Parasitic extraction and mitigation techniques

power integrity , Perl, Shell scripting, Python, Tcl, Physical Design signoff, power grid optimization, Cadence Voltus, electromigration concepts, Ansys RedHawk, static and dynamic IR drop analysis, EM IR analysis

Hydraulic model build verification and calibration, Bentley Water Hammer, Surge Analysis, Autodesk Civil3D, Hydraulic modelling, Report Writing, Bentley WaterGEMS, Water master planning, Autocad, Tender Documentation, Preparation of project specifications

Salesforce Integration, Boomi, Soap, REST, Cti, middleware, Dialer, ACD routing strategies, API-based integrations, omnichannel platforms, Copilot analytics, AI-driven CX capabilities, IVR development, cloud contact center solutions, NICE CXone, virtual agents

redhawk , Tcl Scripting, Python, timing reports, primetime, Fusion Compiler, floorplanning, CTS routing, Tempus, LEC, Cadence Innovus, Physical Verification, setup hold debugging, Voltus, tile block PnR, Calibre, Asic Physical Design, Optimisation, StarRC, Parasitic Extraction, Placement, Synopsys ICC2

Advanced Process Nodes, Custom Layout, EM, Ir, Mentor, LVS, Analog Circuit Design, Physical Verification, ERC, DRC, Siemens, Cadence Virtuoso, Synopsys, Layout Design

Perl, Python, Tcl, Siemens Calibre, PERC, Calibre Interactive, TVF, Cadence Pegasus, EDA visualizer, LVS, CalibreDRV, Calibre DesignRev scripting, DRC, Tk, design for manufacturing, Cadence Virtuoso, SVRF