boundary scan , logic bist , Test Automation, DFT Methodologies, Scan Design, Fault Simulation, ATE Programming, Design Debugging, DFT Architecture, Timing Analysis

Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan

Verilog, Jtag, Dft, MBIST, IEEE1500, IEEE1687, ATPG, Cadence

Scan, HDLs, MBIST, DFT architecture definition, Tempus, ATPG flow implementation, scripting skills in Perl, Genus, tessent DFT, JTAG boundary scan, Cadence digital implementation tools

test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, equivalence check DFT DRC rules, simulating test vectors, ATPG coverage analysis, Cadence Encounter Test, DFTMax, timing fixes corrective actions for timing violations, ASIC DFT

Pre-silicon DFT verification, Post-silicon validation, Yield improvement, BSCAN, Hierarchical multi-core test strategies, MBIST, Scripting and automation, Scan compression, GLS, Power-aware DFT, ATPG simulation, ATPG, Debug, DFT timing closure, LBIST, ATE test program development, Coverage closure, IJTAG, Silicon bring-up

Jtag, Perl, Tcl, Memory BIST, Fusion Compiler, ATPG, AI-assisted workflows, Genus, Scan insertion techniques, Primetime STA, Scan architecture

occ, Memory-BIST, DFT architecture scan Insertion compression at core level and SoC level, SSN architecture, timing and no-timing simulations, clock architecture, ATPG pattern generation coverage analysis