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Senior DFT Engineer
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Senior DFT Engineer
Praxis Hr SolutionsEarly Applicant
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- Posted 17 days ago
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Job Description
Job Summary
- The DFT Engineer will design, implement, and verify state-of-the-art test architectures for complex System-on-Chips (SoCs) and ASICs. You will be responsible for defining the test strategy, executing test insertion, generating high-coverage patterns, and collaborating with post-silicon teams to debug hardware
More Info
Key Skills
DFT Methodologies
Scan Design
ATE Programming
Design Debugging
DFT Architecture
About Company
Skills:
Pre-silicon DFT verification, Post-silicon validation, Yield improvement, BSCAN, Hierarchical multi-core test strategies, MBIST, Scripting and automation, Scan compression, GLS, Power-aware DFT, ATPG simulation, ATPG, Debug, DFT timing closure, LBIST, ATE test program development, Coverage closure, IJTAG, Silicon bring-up
Skills:
occ, Memory-BIST, DFT architecture scan Insertion compression at core level and SoC level, SSN architecture, timing and no-timing simulations, clock architecture, ATPG pattern generation coverage analysis
Skills:
logic bist , DFT architecture, Functional BIST, Digital design flows, Scan compression, SoC MCU architecture, DFT protocols
Skills:
Logic Design, On-chip scan compression, Scan BIST, Fault Simulation, ATPG
Skills:
simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities