Usb, C, Pcie, Verilog, Ethernet, Python, Zebu, Protium, Palladium, systemverilog

Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog

routing, Sta, CTS, ECO execution, Pv, floorplanning, Dfm, constraints synthesis, Dft, Si, Timing Closure, block-level PnR, Netlist to GDS flow

Pcie, LINT, cdc, High-speed protocol, gasket bridge modules, RTL freeze, Dft, RDC, Timing Constraints, Multi Clock Reset Voltage and Power domain, SS LPDDR, Quality Check, SS Ethernet, SoC Chiplet design, SoC IP Design, micro-Architecture specification, SoC Integration, glue logic

Oops, Pytest, L2, L3, System Design, Qos, Python, networking fundamentals, system design patterns, large-scale validation frameworks, test-automation, Acls

I2c, Python, PCB back-end process, DFA, Logic Analyzers, LPDDR4 5, Buck and Boost PMIC, Oscilloscopes, PCIe interface Gen5 Gen6, LDO Load Switch devices, Dfm, SMBus, DC-DC converters, ONFI interface, Power Analyzers, I3C, NAND memories, PCIe analyzers

Low-power Implementation, Physical Verification, Physical Design, Timing Closure, Floor Planning, EDA Tools, Power Grid Design, Power Planning

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog