We are seeking a highly motivated
Principal Engineer Design to lead the physical implementation and timing closure of advanced low-power SoCs targeting the IoT and MCU markets. This role offers the opportunity to drive end-to-end physical design execution, optimize power, performance, and area (PPA), and influence methodology improvements that enable successful silicon delivery.
The ideal candidate will possess deep expertise in physical design, timing convergence, low-power implementation methodologies, and signoff processes while demonstrating strong technical leadership and cross-functional collaboration skills.
Your role
Key responsibilities in your new role
- Lead physical design and timing closure for complex low-power SoCs targeting IoT and MCU applications.
- Manage end-to-end physical implementation from floor planning to final signoff while meeting Power, Performance, and Area (PPA) objectives.
- Drive and optimize die area, timing, power, and performance for both hierarchical block-level and full-chip designs.
- Own critical physical design activities, including package co-design, floor planning, power planning, power grid design, place-and-route (P&R), clock tree synthesis (CTS), timing closure, and physical signoff.
- Ensure successful timing convergence across multiple operating modes and process, voltage, and temperature (PVT) corners.
- Perform and oversee physical verification, signoff validation, and design readiness reviews.
- Collaborate closely with Architecture, RTL Design, DFT, Verification, Packaging, Product Engineering, Foundry, and other cross-functional teams to resolve implementation challenges.
- Drive improvements in EDA tools, design methodologies, automation, and implementation flows to enhance Quality of Results (QoR), productivity, and design efficiency.
- Provide technical leadership in defining physical implementation strategies, risk mitigation plans, and signoff methodologies.
- Mentor and guide engineers, promote technical excellence, and drive adoption of industry best practices across the organization.
Your profile
Qualifications And Skills To Help You Succeed
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related discipline.
- 8+ years of hands-on experience in Physical Design and Timing Closure for complex SoC products.
- Proven success in driving chip implementation from floor planning through tape out and silicon delivery.
- Strong understanding of advanced semiconductor process technologies and associated physical design challenges.
- Experience delivering low-power SoCs for IoT, MCU, consumer, mobile, automotive, or related applications.
Technical Skills & Expertise
- Deep expertise in hierarchical SoC physical design, implementation, and timing convergence.
- Strong proficiency with industry-standard Physical Design, Signoff, and EDA automation tools.
- Hands-on experience in:
- Floor planning and physical partitioning
- Power planning and power grid design
- Place and Route (P&R)
- Clock Tree Synthesis (CTS)
- Static Timing Analysis (STA)
- Multi-mode, multi-corner (MMMC) timing closure
- Physical verification and signoff
- EM/IR and power integrity analysis
- In-depth knowledge of low-power design methodologies and implementation techniques.
- Strong understanding of process technology trade-offs affecting Power, Performance, and Area (PPA).
- Ability to analyze and solve complex implementation challenges through data-driven decision-making and technical collaboration.
Leadership & Collaboration
- Drive technical decisions and take ownership of implementation quality, schedule, and deliverables.
- Collaborate effectively with cross-functional teams across Architecture, RTL, Verification, DFT, Packaging, and Foundry organizations.
- Lead technical discussions, design reviews, and implementation strategy planning.
- Mentor and develop junior engineers while fostering a culture of technical excellence.
- Promote knowledge sharing, best practices, and continuous learning across teams.
- Champion innovation in methodologies, design flows, automation, and tool usage.
- Demonstrate strong communication, stakeholder management, and problem-solving capabilities.
#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in
We are on a journey to create the best Infineon for everyone.
We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity.
Our hiring decisions are based on skills and experience. Even if you don't meet every requirement, we encourage you to apply.
Please let your recruiter know if you need any accommodations during the interview process.
Learn more about our various contact channels and about Diversity & Inclusion at Infineon.
Anand Rawal
