Senior Memory layout Engineer
Senior Memory layout Engineer
smartsoc solutions pvt ltd4-6 Years
- Posted 15 days ago
- Be among the first 10 applicants
Job Description
- Minimum 4+ years of experience with a Bachelor's degree in Engineering studies or Master's degree, strong layout knowledge.
- Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).
- Strong layout knowledge in advanced submicron FinFET processes, including TSMC 5nm, 3nm, 2nm, A14 or Samsung lower FinFET nodes.
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Key Skills
About Company
Skills:
parasitic effects, PEX, Cadence Virtuoso Custom Layout, 5nm FinFET, FinFET layout techniques, matching symmetry, LVS, memory custom layout, design-rule requirements, shielding guard rings, SRAM bitcell memory arrays, layout optimization, ERC, DRC, parasitic optimization, sensitive-net routing, Calibre PVS, advanced-node tapeout