Senior Digital Design Engineer

Job Position : Synthesis & Front-End Implementation Engineer

Job Description

We are seeking a highly motivated Synthesis & Front-End Implementation Engineer to join our dynamic team. In this role, you will be crucial in translating RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks.

Job Responsibilities

As a Synthesis & Front-End Implementation Engineer, your responsibilities will include:

. Performing synthesis of RTL designs for various digital blocks and sub-systems, including hierarchical synthesis methodologies.
. Developing and implementing robust timing constraints (SDC) to achieve target frequencies and optimize design performance.
. Conducting STA, identifying critical paths, and collaborating with design teams for timing closure.
. Executing formal verification (LEC) to ensure functional equivalency between RTL and synthesized netlists.
. Analyzing and optimizing power consumption at the front-end stage, utilizing power analysis tools and techniques.
. Performing area estimation and optimization to meet aggressive chip size requirements.
. Collaborating closely with RTL designers, DFT engineers, and physical design engineers to ensure seamless integration and hand-off.
. Developing and maintaining automation scripts (Tcl, Python, Perl) for synthesis flows and design analysis.
. Evaluating and integrating new CAD tools and methodologies to improve efficiency and design quality.
. Documenting design constraints, methodologies, and analysis results thoroughly.

Job Qualifications

To be successful in this role, you should possess the following qualifications:

. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
. 5+ years of relevant experience in digital ASIC/SoC design, with a focus on synthesis and front-end implementation.
. Proficiency with industry-standard synthesis tools (e.g., Synopsys Design Compiler, Synopsys Fusion Compiler or similar).
. Strong understanding of static timing analysis (STA) concepts and tool (e.g., Synopsys PrimeTime).
. Experience with formal verification tools (e.g., Synopsys Formality, Cadence Conformal (LEC)).

. Understanding of upf, low-power design techniques and power analysis concepts.
. Solid knowledge of Verilog/System verilog for digital design.
. Familiarity with scripting languages (Tcl, Python, Perl) for automation.
. Knowledge of DFT (Design for Testability) principles is a plus.
. Excellent problem-solving skills and attention to detail.
. Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment across multiple time zones.