Analog layout Engineer
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Job Description
At Best Nanotech, we are pushing the boundaries of high-performance analog/mixed-signal design. We are currently seeking a highly experienced Senior Analog Layout Engineer to join our growing team in Bengaluru.
This is a senior-level role requiring deep technical expertise in advanced process nodes and the ability to lead complex layout activities from initial floorplanning to final tape-out.
Position: Senior Analog Layout Engineer
Experience: 7+ Years
Location: Bengaluru
Key Responsibilities
7+ years of hands-on analog layout experience.
Expert proficiency with Cadence Virtuoso XL/GXL and Mentor Calibre.
Proven track record of successful tape-outs in FinFET technologies.
Deep understanding of analog layout concepts: common-centroid matching, shielding, guard-ringing, and latch-up prevention.
Experience with top-level integration and floorplanning challenges.
If you are a seasoned layout professional looking to take ownership of challenging designs, we want to hear from you.
This is a senior-level role requiring deep technical expertise in advanced process nodes and the ability to lead complex layout activities from initial floorplanning to final tape-out.
Position: Senior Analog Layout Engineer
Experience: 7+ Years
Location: Bengaluru
Key Responsibilities
- Lead the physical design of complex analog mixed-signal blocks (e.g., SerDes, PLL, ADC/DAC, PMIC, High-speed I/Os) in advanced FinFET nodes (7nm/5nm/3nm).
- Collaborate closely with circuit designers to optimize layout for performance, focusing on matching, parasitics, EM/IR drop, and signal integrity.
- Own top-level floorplanning, block integration, and power grid redistribution layers (RDL).
- Drive the physical verification process (DRC, LVS, ERC, ANT) using Calibre and resolve complex violations.
- Mentor junior layout engineers, define layout methodologies, and improve design flow efficiency.
7+ years of hands-on analog layout experience.
Expert proficiency with Cadence Virtuoso XL/GXL and Mentor Calibre.
Proven track record of successful tape-outs in FinFET technologies.
Deep understanding of analog layout concepts: common-centroid matching, shielding, guard-ringing, and latch-up prevention.
Experience with top-level integration and floorplanning challenges.
If you are a seasoned layout professional looking to take ownership of challenging designs, we want to hear from you.
More Info
Key Skills
analog layout concepts
Mentor Calibre
Cadence Virtuoso XL
FinFET technologies
About Company
Skills:
FinFET GAA layout concepts, Cadence Virtuoso Custom Layout, PEX and post-layout simulation correlation, matching shielding guard rings isolation and parasitic optimization, Calibre PVS, advanced-node analog custom layout
Skills:
ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques
Skills:
High-speed SERDES IO PHY Layout design, Analog IO design principles, Signal integrity issues, Automated PnR, CMOS and FinFET technologies
Skills:
Cadence Tools, FinFET process technologies, DRC LVS checking flows with Calibre