Physical Design, Design for manufacturability, Timing closure methodologies, Placement and routing techniques, Clock Tree Synthesis, Design rule checks

PYTHON, routing, PERL, Tcl, power analysis, physical design methodology, LVS, Physical Verification, noise analysis, Logic Synthesis, DRC, electro migration, Placement, Clock Tree Synthesis

hardware engineering , Static Timing Analysis (STA), Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation

Routing, Sta, CTS, floorplanning, EM, Ir, LVS, Physical Implementation, RTL-to-GDSII flow, Synthesis, Physical Design, Placement, Si, DRC

C, Perl, Tcl, C++, Routing, Clock Planning, Physical Verification, floorplanning, Timing Closure, Physical Design Implementation, Innovus, Calibre, primetime, Placement, ICC2, LEC, EDA Tools

Physical Design Planning, Placement, Floor Planning