rtl verification , Automation, Verilog, Python, FineSim, AMS verification, Transistor-level verification, Mixed-signal coverage analysis, AI-assisted solutions, Circuit Analysis, Uvm, Functional code assertion, systemverilog, CMOS design fundamentals, Hspice, Mixed-signal architectures, Semiconductor device behavior, Spice, EDA workflow optimization

bandgap references , temperature sensors , frequency response, Sigma-Delta converters, mismatch analysis, op-amps, AMs, precision analog circuits, ip development, AC simulations, Layout XL, ADEXL, Cadence Virtuoso suite, Schematic Maestro, mixed-signal circuit design, DC operating point, biasing circuits, noise, INL, Spectre, DNL, Stability, CMOS technologies, LDOs, THD

UNIX, Layout tradeoffs, End to end design flow, CMOS BiCMOS fabrication processes, Modeling Tools, MOS transistors, Analog Circuit Design, Poles zeros compensation, Signals systems and transforms, Mixed Signal Design, Production test applications, Feedback systems, device physics, Circuit simulation tools, AC DC analysis, Loop dynamics, Analog Power IC design, Layout verification tools

System Integration, Matlab, IC System Partitioning, Routing Tradeoffs, Physical Layout Management, Signal Grounding, Block-level Modeling, Architectural Tradeoff Analysis, AMs, Spectre, Worst-case Identification, Monte Carlo Analysis, Device Physics Knowledge, Simplis, Post-layout Parasitic Extraction, Block-level Topology Selection, Top-level Verification, Schematic Generation

Perl, Verilog, Python, scripting and automation tools, ISO26262, Formal verification methodologies, ADCs, Cadence, Automotive qualification, Uvm, systemverilog, Analog Circuit Design, DACs, Comparators, Op-Amps