Pcie, Perl, Vcs, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog

Verification IP (VIP) Integration, Universal Verification Methodology (UVM), System Verilog, Python, SystemVerilog Assertions, scripting languages such as Perl, SV UVM environments, debugging RTL TB issues using Verdi, Functional Code Coverage, constraint random tests, HDLs like Verilog, Formal checks, Functional Verification, SoC Integration

code coverage , Cpu, Usb, Oops, Verilog, Arm, Networking, Ethernet, Pcie, DDR, AHB, spyglass, LINT, SV, Graphics, SoC Verification, cdc, AMBA, RTL Coding, VHDL, C tests, SV METH, Axi

Test Case Creation, Python, Perl, Shell, Formal Verification techniques, Advanced Debugging skills, Uvm, Rtl Design, testbench development, coverage-driven verification, Computer Architecture concepts, Functional Verification