Unix, Lsf, Constraints, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, CI/CD, Low Power, Slurm

Circuit Card Assembly (CCA) Design, Usb, Ethernet, I2c, MIL-STD-461 Testing, Requirements Capture and Traceability, Signal Integrity Analysis, schematic capture, Troubleshooting using engineering laboratory equipment, Digital Electronics Design, DDR3 Memory Interfaces, Timing Analysis, SERDES Interfaces, LVDS, DO-160 Testing, MIL-STD-810 Testing

Emulation, SoC design methodology, silicon bring-up, Microarchitecture, Timing Analysis, Synthesis, Physical Design, RISC CPU IP, Verification, Rtl Design

Object Oriented Programming, Shell, Perl, Python, Make file, Power aware verification, Gate-Level Simulation, System Verilog UVM, Mentor, Cadence, UPF, C based and assembly level testcases, Assertions, System Verilog Testbench Architecture, HDL such as Verilog SystemVerilog, Processor Architecture, Processor Verification, HVL such as SystemVerilog testbench OVM UVM, TCI, Synopsys, formal verification, Digital Design

Tcl, Python, Perl, Innovus, Physical Formal Verification, Cross-Functional Collaboration, LEC, primetime, EDA Tools, Fusion Compiler, Calibre, Red Hawk, Tempus, Timing Closure STA, RTL-to-GDSII Execution, Programming Scripting, VCLP, PPA Optimization

static timing analysis, Perl, shell scripting, Python, Tcl, LINT, Synthesis, cdc, SoC integration, UPF-based methodologies, ASIC SOC design, systemverilog, Dft, RTL Verilog, Bluetooth SoCs, low-power design

Static Timing Analysis (STA), PERL, Python, Tcl, Synthesis, Cadence