C, C++, Python, Ethernet protocol verification, SystemVerilog UVM, MAC PCS Ethernet PHY interfaces, constrained-random verification, verification automation, assertions, compliance verification, SerDes controller verification, simulation waveform analysis, functional coverage

Gdb, Verilog, Python, Perl, Indago, SV scripting languages, Cadence

arm architecture , ACE lite or CHI bus protocols, CPU architecture, Coherent and non-coherent fabric IPs and protocols, PCIe Controller PHY IPs and protocols, DDR protocols, emulation constraints, pre-silicon SoC verification, Memory Controller PHY IPs, performance verification

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Ovm, Debugging, Test Planning, CHI, SoC design verification, AMBA protocols, Uvm, UVM-based test benches, system simulation tools, Axi, APB, emulation models, AHB

Uart, Usb, Regression Testing, C Programming, Ethernet, SVA, Assertions, Uvm, UPF, Functional Coverage, systemverilog, AMBA Protocols, AHB, CPF, APB, Axi, ARM-based SoC Verification

Uart, Usb, Tcl, Ethernet, Perl, Spi, I2c, Shell Scripting, Python, DDR, AHB, UCIe, Siemens QuestaSim, Functional Coverage, systemverilog, MIPI, CXL, DVE, APB, Axi, Cadence Xcelium, Uvm, Constrained Random Verification, Scoreboards, Verdi, Functional Checkers, Synopsys VCS

Debugging, Uvm, Test Planning and Strategy, systemverilog, Mixed-Signal Verification