Perl, Python, SV, low power simulations, Uvm, testbench development, debugging gate level simulations, Axi, APB, BUS Protocols, assertions coding, AHB

Gdb, Verilog, Python, Perl, Indago, SV scripting languages, Cadence

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Uart, Usb, Regression Testing, C Programming, Ethernet, SVA, Assertions, Uvm, UPF, Functional Coverage, systemverilog, AMBA Protocols, AHB, CPF, APB, Axi, ARM-based SoC Verification

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Bus protocols - APB, C, Usb, Uart, Spi, Test Plan Creation, Pcie, I2c, System Verilog, Bus interconnects, Checkers, i2s, Uvm, Functional coverage, DP, Sd, AHB, Verification methodology, Gate-level simulations, Scoreboards, Gate Level Power-Aware simulations, Axi

Uart, Usb, Tcl, Ethernet, Perl, Spi, I2c, Shell Scripting, Python, DDR, AHB, UCIe, Siemens QuestaSim, Functional Coverage, systemverilog, MIPI, CXL, DVE, APB, Axi, Cadence Xcelium, Uvm, Constrained Random Verification, Scoreboards, Verdi, Functional Checkers, Synopsys VCS

Verilog, Gdb, Perl, Python, SV-UVM, e-specman, SV, Indago, Cadence, Verification fundamentals

Perl, Python, Formal Verification methodologies, Axi, APB, JasperGold, AMBA protocols, VC Formal, Uvm, AHB, systemverilog

Debugging, Uvm, Test Planning and Strategy, systemverilog, Mixed-Signal Verification