Perl, Python, Tcl, Skill, Calibre PVS, mixed-signal layout, Cadence Virtuoso

hardware engineering , C, Jtag, Verilog, Scripting Languages, System Verilog, IEEE1500, HDLs, memory dump, MBIST, scan dump, formal verification methodologies, CPU micro-architectures, CPU architectures, power management features, testbench components

Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage

python, Perl, System Verilog, test plans for DDR LPDDR IP verification, DDR-IO verification, debug and problem solving, LPDDR JDEC specifications, system verilog programming, coverage driven verification methodology, Uvm

Java, Pcie, Perl, Verilog, Python, System Verilog, coverage-based verification methodology, assertions, Intel Quartus, Uvm, Xilinx Vivado

Uart, Usb, Tcl, Ethernet, Perl, Spi, I2c, Shell Scripting, Python, DDR, AHB, UCIe, Siemens QuestaSim, Functional Coverage, systemverilog, MIPI, CXL, DVE, APB, Axi, Cadence Xcelium, Uvm, Constrained Random Verification, Scoreboards, Verdi, Functional Checkers, Synopsys VCS

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

Java, Data Modeling, API design, Sql, Microservices, Nosql, System Design, Distributed Systems, RESTful, Python, Event-driven architecture, Go, GRPC, Caching solutions