Nvme, SAS, Silicon Validation, Pcie, physical implementation, Synthesis, tape-out processes, RTL design using Verilog, Uvm, systemverilog, Dft, Timing Closure, CXL

Fpga, Perl, Python, Tcl, Sta, place-and-route, Synthesis, cdc, LINT, power analysis, UPF, Dft, RDC, digital design verification and implementation tools, Low Power design techniques, RTL coding techniques

Veeva, Sas Programming, Database Management, Forms Design, Gcp, EMA, risk management, Database Setup, Fda, edit check programming, ICH Guidelines, Operational Management, Study Startup, EDC build lifecycle, Clinical Data Management, Data Review, Medidata Rave, portfolio governance

Silicon Validation, Soc Architecture, Physical Design, manufacturing, digital design verification, Dft

biostatistics , cdms , Ml, Hl7, SAS, Python, Sycamore, Medidata Rave, Domino, Ai, GenAI, ctms, epro, Oracle InForm, EDC Platforms, USDM, SAS Viya, statistical programming, LSAF, Clinical Data Management, Nurocor, FHIR, R, Clinical Data Standards, Formedix, eClinical Elluminate, eTMF, Oracle LSH, Veeva EDC

Peripheral subsystems, Assertions, UVM-based test plan development, HSIO, SoC-level verification, Integration of multiple IPs, Verification infrastructures, coverage analysis

Ecos, Clock Reset UPF, IP integration, FCR ECR reviews, timing convergence, RTL construction, SOC design

Ecos, SoC DV test plans, RTL construction, FCR ECR reviews, PPA targets, SOC design, Fuse Documentation, Clock Reset UPF, constraint and timing convergence, IP integration