FinFET GAA layout concepts, Cadence Virtuoso Custom Layout, PEX and post-layout simulation correlation, matching shielding guard rings isolation and parasitic optimization, Calibre PVS, advanced-node analog custom layout

Synopsys IC Validator, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, Cadence Pegasus, high-speed analog and mixed-signal layout design, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, DRC, parasitic optimization, reliability rules

Routing, Pvs, PERL, Tcl, R3D, PEX, LVS, Layout Techniques, Verification, Skill Programming, CAD Tools, Calibre, Analog Layout, ERC, VCAR, DRC, VSR, virtuoso