virtualization, Memory Management, Perl, Python, System Verilog, IP Sub System design verification, Functional Coverage, Trackers, Assertion, Checkers, HW-SW debug, Uvm, power management fundamentals, coherency protocols, DV test bench, Scoreboards, Post-Silicon bring-up, Virtual Memory concepts

Java, Kafka, Python, API design, Incident Management, Gcp, Distributed Systems, Kubernetes, Testing, Go, Alerting systems, Flink, Microservices architecture, developer tools, Streaming Data, SDKs, Monitoring

C, Perl, Arm, Python, Digital multi core SoC verification, Cadence SKILL, Mixed-signal Verification, Uvm, systemverilog, UVM testbench creation, RISC-V Assembly, RN Real Number Digital top-level modeling

power integrity , Perl, Python, Tcl, FinFET process technologies, Ansys RedHawk-SC, Quantus PrimePower, Cadence Voltus, physical-design implementation, Joules, EMIR analysis, StarRC, current and activity models

Ansys, Silicon Validation, PERL, Debugging, Python, analog simulation, lab equipment, Cadence, Analog Circuit Design, design for test, Mixed Signal Design, EDA Tools, CMOS technology, silicon bring-up, virtuoso, Synopsys, low-power design techniques

Excel, Python, Ms Word