Fpga, Logic Design, Verilog, Sta, Synthesis, Power product design, TCL scripts, Scan Insertion, Timing Analysis, design constraints, Uvm, ATPG generation, regression frameworks, formal verification, Timing Constraints, synthesis scripts, ABV, RTL Coding, micro-architecture, Functional Verification, System-Verilog, Digital Verification

Tcl, Shell scripting, Python, Perl, Debugging, Uvm, systemverilog, Mixed-Signal Verification

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog