test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, equivalence check DFT DRC rules, simulating test vectors, ATPG coverage analysis, Cadence Encounter Test, DFTMax, timing fixes corrective actions for timing violations, ASIC DFT

redhawk , Tcl Scripting, Python, timing reports, primetime, Fusion Compiler, floorplanning, CTS routing, Tempus, LEC, Cadence Innovus, Physical Verification, setup hold debugging, Voltus, tile block PnR, Calibre, Asic Physical Design, Optimisation, StarRC, Parasitic Extraction, Placement, Synopsys ICC2

Multi-mode multi-corner (MMMC) timing closure, Network-on-Chips (NoC), System IP components, Physical design implementation, floorplanning, Uncore subsystems, Timing budgeting, Place-and-route, Coherent CPU clusters, Timing Closure, Synthesis, RTL-to-GDSII implementation, Partitioning, Hierarchical design techniques, Sign-off

power integrity , Perl, Shell scripting, Python, Tcl, Physical Design signoff, power grid optimization, Cadence Voltus, electromigration concepts, Ansys RedHawk, static and dynamic IR drop analysis, EM IR analysis

conformal lec , Python Scripting, Verilog, primetime, Fusion Compiler, Genus, Tempus, CPF, UPF, DFT insertion

Quality, Poka-Yoke, Welding, Continuous Improvement, Ppc, Production Fabrication, Production Planning, Heavy Fabrication, Maintenance, Machine Shop Processes, Painting, Jigs, Shop Floor Production Management, Contract Manpower Management, Kaizen, Fixtures, Safety Standards, Manpower Handling, Scm