boundary scan , Vcs, Python, Perl, Tcl, sdf debugging, Scan Insertion, DFT CAD development, Jtag protocols, DFT logic IP integration, p1687, p1500, EDA Tools, BIST architectures, Test static timing analysis, Tessent tool sets, Test Architecture Methodology, Infrastructure, memory BIST, TetraMax, Verilog design, Functional Verification, Gate level simulation, ATPG, Timing Closure, timing based simulations, TestMax

System Verilog, Post-silicon validation, Logic Equivalency checking, JTAG protocols, ATPG, Scan and BIST architectures

System Verilog, Vcs, Tessent, primetime, Logic Equivalency checking, TestMax, EDA Tools, JTAG protocols, ATPG, Scan and BIST architectures, TetraMax

data streaming , Github, Apis, Data Modeling, PostgreSQL, Performance Tuning, Pyspark, Pl Sql, Autosys, Db Design, Sql, Unix Shell Scripting, Agile Software Development, Apache Kafka, Oracle, Python, AWS, Airflow, NoSQL databases, Data Bricks

Java, Scala, Node.JS, Python, Advanced prompt engineering skills, Large-scale system architecture, Agile Scrum methodologies, Go, AI-first approach to engineering, Full-stack software development