Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

Tcl Scripting, Doors, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, DO-254 development process, Electronics Electrical Engineering, Hardware system design knowledge of digital logic, RTL development using VHDL, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Requirement analysis and validation, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero

DDR, Usb, Pcie, Ethernet, SV, CXL, Uvm

Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus

Fpga, Usb, Python, Pcie, Perl, Emulation, directed constrained-random tests, Uvm, AXI4, coverage driven verification, Test Bench, verification methodologies, systemverilog, transaction level modeling, AMBA, MIPI, formal verification

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog

Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA

Verilog, System Verilog, Asic verification, Uvm, cpu design, DDR4, Memory

Verilog, System Verilog, VHDL, Xcelium, Questa, Simulator exposure with VCS, Proficient in simulation and HW languages, Uvm, UVVM

Doors, Tcl Scripting, FPGA Synthesis Place and Route, DO-254 development process, RTL development using VHDL, Hardware system design knowledge of digital logic, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, FPGA design tools like Libero, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory