Perl, Python, Tcl, Skill, Calibre PVS, mixed-signal layout, Cadence Virtuoso

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, Uvm, systemverilog, Scoreboarding, Performance bottleneck analysis, Simulation-based verification, IP-level verification, coverage analysis, Regression, Performance verification, Functional coverage, Assertions, Constrained-random verification, Testbench architecture, Coverage closure, SVA, formal verification, Reference models

arm architecture , Usb, DDR, Perl, Pcie, Test Plan, Scripting, Python, Shell Programming, Tcl, Arm core, GIC, SMMU, Dms, verification checks, Arm system IP, verification plan, debug methodology, SoC Verification

temperature sensors , System Design, High Voltage charge pumps, Analog IP design, Silicon Characterization, Oscillators, ADCs, Probing, DC-DC converter, Current and Voltage reference, EDA Tools, Switch capacitor circuits, LDO, Voltage regulators