code coverage , C, Shell, Perl, Verilog, Debugging, Python, System Verilog, Tcl, UVM methodology, Metric Driven Verification, formal verification methodologies, assertions, constrained random methodologies, functional coverage

Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage

Perl, Python, Sequencers, Agents, Checkers, Uvm, Functional coverage, systemverilog, Assertions, Coverage models, Verilog-AMS, Verification methodology, Scoreboards, Monitors, Constrained random techniques, Verilog-A

C, Uart, Bash, Spi, DDR, Perl, Pcie, Verilog, I2c, Python, System Verilog, Tcl, i2s, DFX Verification, Uvm, Axi, APB, AHB

C, Pcie, Perl, Python, Tcl, ONFI, LPDDR, NAND

arm architecture , Random Instruction Sequences (RIS) tool, Assembly language (ASM), C, C++, Software Design, Hardware Design Verification, EDA Tools, CPU micro-architecture

Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA

Perl, Python, Tcl, Siemens Calibre, PERC, Calibre Interactive, TVF, Cadence Pegasus, EDA visualizer, LVS, CalibreDRV, Calibre DesignRev scripting, DRC, Tk, design for manufacturing, Cadence Virtuoso, SVRF

C, Perl, Verilog, Shell scripting, Python, Tcl, EDA toolkits, UVM assertions, SVA, systemverilog