Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Signal Integrity, Leakage Power, Multi-Vt Flow, Dfm, IC design, Power Supply Management, Deep Sub-Micron Design Problems, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

Ecos, routing, Perl, Python, Tcl, Sta, Synthesis, Design Compiler, CTS, primetime, Fusion Compiler, floorplanning, Asic Physical Design, setup hold closure, Placement, MCMM timing analysis, Synopsys ICC2

power optimization , routing, Perl, Verilog, Python, Tcl, Synthesis, submicron process node technologies, Timing Analysis, power delivery methodologies, LVS, Power Estimation, formal verification, VHDL, layout verification methods, DRC, Placement, low-power design techniques, timing signoff, Clock Tree Synthesis

cadence encounter , Unix, Shell, Linux, Flow automation, Synopsys ICC2 tool set, Skill, 10nm 7nm 5nm process nodes, Tapeout sign-off experience, Python Script, SDC STA and Equivalence checking, Physical Design, PnR tools like ICC2 Innovus

Power Planning, Routing optimization, floorplanning, Placement, Debugging setup hold violations, Physical Verification, Physical Design ASIC implementation, Cadence Innovus