code coverage , Regression Analysis, Test Plan Creation, formal verification, SV assertions, Uvm, coverage-driven verification, systemverilog, functional coverage

arm architecture , C, Ovm, Jtag, Perl, Verilog, System Verilog, Python, CPU architecture, interconnects, Uvm, debug architecture protocols, power management techniques, coherent fabrics, VHDL, SoC Verification, SVTB

Low Power Verification., C Programming, SoC Verification, systemverilog, Uvm, ARM SoC, Gate Level Simulation, Coverage Closure, APB, AHB, Axi

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Debugging Tools, Tcl, Python, Perl, LPDDR5, DDR4, Uvm, DDR protocols, DDR5, systemverilog, AHB, LPDDR4, Axi, DDR verification

Regression Testing, Usb, Uart, C Programming, Ethernet, Functional Coverage, Uvm, UPF, systemverilog, Assertions, Axi, APB, AMBA Protocols, CPF, AHB, SVA, ARM-based SoC Verification

Perl, Verilog, Python, advanced verification methodologies like e-specman SV-UVM, debug tools like Indago GDB, SV scripting languages, Cadence or equivalent simulation tools

C, Noc, Python, Pcie, Perl, Soc Architecture, Coherency verification, Reset and power verification, Uvm, SOC bring-up, Post-silicon validation, AHB, Bus Fabric, UPF integration, SOC verification methodologies, HW FW interaction verification, Axi

Verilog, Debugging, Automation Scripting, formal verification, AI-assisted Workflows, Protocol Verification, Property Checking, SVA, systemverilog, Equivalence Checking, Formal Analysis

Test Plan Creation, Regression Analysis, SV assertions, Formal verification methods, Uvm, Coverage-driven verification, systemverilog