Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, SystemVerilog UVM, Axi, CXL, SVA

Pcie, Ethernet, Python, characterization NRZ and PAM-4, Network Analyzers, Communication Protocols, high-speed SerDes validation, Oscilloscopes, BERTs, DCAs

Excel, Python, Ms Word

Fpga, Perl, Python, low power verification, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, RTL development environments, test bench infrastructure, transaction level modelling, verification platforms, formal verification methods, emulation platforms

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Tcl Scripting, Doors, DO-254 development process, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, RTL development using VHDL, Hardware system design knowledge of digital logic, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero