synopsys tools , Scripting, Soc Architecture, Physical Design, design validation, Microarchitecture, Design Principles

Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Signal Integrity, Leakage Power, Multi-Vt Flow, Dfm, IC design, Power Supply Management, Deep Sub-Micron Design Problems, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, low-power design techniques, Place And Route, Clock Tree Synthesis

Ecos, routing, Perl, Python, Tcl, Sta, Synthesis, Design Compiler, CTS, primetime, Fusion Compiler, floorplanning, Asic Physical Design, setup hold closure, Placement, MCMM timing analysis, Synopsys ICC2

Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, AI-assisted Tools, NDM Liberty, MemView Generation, LEF, PVT Corner Coverage

NDM Liberty .lib, Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, MemView Generation, LEF, PVT Corner Coverage

cadence encounter , Unix, Shell, Linux, Flow automation, Synopsys ICC2 tool set, Skill, 10nm 7nm 5nm process nodes, Tapeout sign-off experience, Python Script, SDC STA and Equivalence checking, Physical Design, PnR tools like ICC2 Innovus

Power Planning, Routing optimization, floorplanning, Placement, Debugging setup hold violations, Physical Verification, Physical Design ASIC implementation, Cadence Innovus