C, Spi, Verilog, I2c, Python, C++, Uart, Perl, Real Number Modeling, LNA, Analog IC design, LVS, Bias bandgap, VHDL, Cadence IC design tools, Filters, LDO, Layout experience using Cadence flow, VerilogAMS, Charge pump, Opamp, systemverilog, MIPI, DRC, VerilogA

Matlab, Worst case identification, Monte Carlo analysis, Block level topology selection, AMs, Analog Circuit Design, Spectre, Cadence tool set, Top level simulation, Simplis, IC system partitioning and architectural tradeoff analysis, Hand analysis and IC transistor level implementation, Post layout parasitic extraction, Schematic generation and simulation on modern CAD tools

cadence spectre , mosfet , Synopsys tool suites, aging effects, small-signal modeling, jitter, BJT device physics, crosstalk, Verilog-AMS, Mentor Graphics, Cadence Virtuoso, Verilog-A, thermal noise