Usb, C, Pcie, Verilog, Ethernet, Python, Zebu, Protium, Palladium, systemverilog

Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog

Perl, Vcs, Python, Tcl, Incisive, Verdi, DVE, Questa, Uvm, systemverilog

Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA

C, Perl, Arm, Python, RISC-V Assembly, digital Verification, Cadence SKILL, Mixed-signal Verification, Uvm, systemverilog, UVM testbench creation

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, Ace, RISC-V, ARM CPU, Uvm, systemverilog, Axi, CXL, SVA