Ovm, Debugging, Test Planning, CHI, SoC design verification, AMBA protocols, Uvm, UVM-based test benches, system simulation tools, Axi, APB, emulation models, AHB

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

C, Fpga, Verilog, verification infrastructure, verification testbenches, SW simulators, systemverilog

code coverage , Regression Analysis, Test Plan Creation, formal verification, SV assertions, Uvm, coverage-driven verification, systemverilog, functional coverage

arm architecture , C, Ovm, Jtag, Perl, Verilog, System Verilog, Python, CPU architecture, interconnects, Uvm, debug architecture protocols, power management techniques, coherent fabrics, VHDL, SoC Verification, SVTB

Low Power Verification., C Programming, SoC Verification, systemverilog, Uvm, ARM SoC, Gate Level Simulation, Coverage Closure, APB, AHB, Axi

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Debugging Tools, Tcl, Python, Perl, LPDDR5, DDR4, Uvm, DDR protocols, DDR5, systemverilog, AHB, LPDDR4, Axi, DDR verification