C, Fpga, Verilog, verification infrastructure, verification testbenches, SW simulators, systemverilog

arm architecture , C, Ovm, Jtag, Perl, Verilog, System Verilog, Python, CPU architecture, interconnects, Uvm, debug architecture protocols, power management techniques, coherent fabrics, VHDL, SoC Verification, SVTB

Low Power Verification., C Programming, SoC Verification, systemverilog, Uvm, ARM SoC, Gate Level Simulation, Coverage Closure, APB, AHB, Axi

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Debugging Tools, Tcl, Python, Perl, LPDDR5, DDR4, Uvm, DDR protocols, DDR5, systemverilog, AHB, LPDDR4, Axi, DDR verification

Regression Testing, Usb, Uart, C Programming, Ethernet, Functional Coverage, Uvm, UPF, systemverilog, Assertions, Axi, APB, AMBA Protocols, CPF, AHB, SVA, ARM-based SoC Verification

Test Plan Creation, Regression Analysis, Uvm, formal verification, coverage-driven verification, systemverilog, SV assertions