Tcl, C, Perl, Physical Verification, Timing Closure, floorplanning, Physical Design Implementation, Clock Planning, Placement and Routing

Perl Scripting, Tcl, PDN Methodology, Leakage Power, Dfm, Power Supply Management, Circuit Level Comprehension, PPA Targets, RTL to GDSII Implementation, High Frequency Design, Deep Sub-Micron Design, Sta, Signal Integrity, Power Gating, Physical Design, Timing Signoff, IC design, Multi-Vt Flow, Hardware